1. Technical Field
The present disclosure relates to integrated circuit (IC) design, and more specifically to an IC design flow which incorporates optimal assumptions of power supply voltage drops at cells contained in the IC, when performing timing analysis for the IC.
2. Related Art
An Integrated Circuit (IC) design flow generally refers to the various phases involved in designing an IC, with one or more of the phases being typically performed using electronic design automation (EDA) or computer aided design (CAD) tools. Some examples of the various phases (or steps) include functional description, synthesis, and timing analysis (timing closure), power supply drop (IR drop analysis), etc.
Power supply and ground connections to each component (cell) in the IC may be provided using one of several known approaches (for example via power supply and ground grids). As is well known in the relevant arts, the magnitude of the power supply provided to (i.e., available at) a cell may vary from desired (ideal) values due to voltage drops in the paths used to provide (or route) the power supply and ground connections to the cell.
Such power supply voltage drops generally cause the speed of operation (input signal received to output signal generation) of the cell to vary, with the speed variation generally having a positive correlation with the power supply voltage.
Such speed variations due to power supply drops may need to be taken into account when performing timing analysis for the IC. As is well known in the relevant arts, timing analysis generally refers to the process of verifying whether various timing parameters such as setup and hold timing, logic delay etc., at circuit nodes (e.g., inputs/outputs of cells) of the IC are satisfied or not for a desired operating speed (often indicated by the frequency of a clock(s) used to control the operation of various portions of the IC).
Hence, a measure of the magnitude of the voltage drops at each of the cells of the IC is often required when performing such timing analysis. Further, the voltage drops used in performing the timing analysis may need to be selected (or assumed) in an optimal manner such that optimum area and/or speed may be obtained for the IC, along with reduced design time, minimal computing and storage resources for the design flow, etc.